Difference between revisions of "LP module"
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| − | = LogicPool ( | + | = LogicPool (TEMPLATE) = |
This VHDL module needs a SU7XX hardware sub-module to work. | This VHDL module needs a SU7XX hardware sub-module to work. | ||
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|- | |- | ||
| 0 | | 0 | ||
| − | | VERSION | + | | VERSION, MODEL and Driver if any |
| − | | Bit 7..0: | + | | |
| + | Bit 31..25: VERSION HI | ||
| + | Bit 24..16: VERSION LOW | ||
| + | Bit 15..8 : MODEL | ||
| + | Bit 7: Status | ||
| + | Bit 6..0: Driver | ||
|- | |- | ||
| 17 | | 17 | ||
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== LabVIEW Vi == | == LabVIEW Vi == | ||
| − | === | + | === TEMPLATE.vi === |
| − | + | ||
| + | Template VI for new designs | ||
[[File:DO__HVc.png]] | [[File:DO__HVc.png]] | ||
| − | + | Introduction. | |
| + | |||
| + | The meaning of almost inputs and outputs of this Vi depends on the input "Function". The global inputs and outputs does not depend on the "function" input: | ||
=== Glogal Inputs === | === Glogal Inputs === | ||
Latest revision as of 12:19, 3 May 2016
Contents
LogicPool (TEMPLATE)
This VHDL module needs a SU7XX hardware sub-module to work.
Models
There is only one model for this module.
Supported Hardware
Register Map
Module Address: 'C' or OxFF
Read register
| Register Address | Name | Data |
|---|---|---|
| 0 | VERSION, MODEL and Driver if any |
Bit 31..25: VERSION HI Bit 24..16: VERSION LOW Bit 15..8 : MODEL Bit 7: Status Bit 6..0: Driver |
| 17 | Status | MAX14900E status, 15..8 F8..F1, 7..0 S8..1
F_ S_ O_ Status 0 s No fault detected, logic state of O_ is s 1 0 Fault detected, logic state not defined 1 1 Under voltage lockout detected |
Write register
| Register Address | Name | Data |
|---|---|---|
| 0-9 | Input Driver | Bit 7..0: Select the input driver of each output |
Read/Write register
| Register Address | Name | Data |
|---|---|---|
| 16 | CONFIG | Bit 9..0: output register
Bit 25..16: direct input mask |
| 18 | Serial configuration | Serial Config, 15..8 C18..C11, 7..0 C08..C01
Ignored if PUSHPL is high! C1_ C0_ O_ Config OLD 0 High-side mode, open-load detect=OLD X 1 Push-pull mode |
| 19 | Parallel configuration |
Bit 3: PUSHPL - this is the global pin, if low, then can be set pin by pin using SPI
high means the outputs 7..0 are push-pull, low - depending on the serial config
Bit 2: unused
Bit 1: SRIAL - low for parallel mode, hardwired now!
Bit 0: global enable for outputs 7..0 (8..1)
|
LabVIEW Vi
TEMPLATE.vi
Template VI for new designs
Introduction.
The meaning of almost inputs and outputs of this Vi depends on the input "Function". The global inputs and outputs does not depend on the "function" input:
Glogal Inputs
DIO_HV#: number of HV digital output to be accesed (1..255).
USB In: Handle to the LogicBox (create by open.vi), if not connected will take a global. parameter, this only works with one LogicBox at a time.
error in: error handling input
Global Outputs
USB out: Handle to the LogicBox.
error out: error handling output
Functions
Connect: enable, configurate and set input/value of the HV digital output.
Inputs:
"DO" : set the signal number which will drive the output, this signal can be set or clear
manually using the module "B_S.vi" (Bool to Signal).
"DI" : get the signal number of which drives this input.
Get Status: the cicuitry of the digital output can detect two errors, under voltage or logic state
undifined. Only the first 8 channels support this features
Input: "Channel": number of channel to be configured
Output: Output Status
Set DO: set the signal number which will drive the output, this signal can be set or clear manually
using the module "B_S.vi" (Bool to Signal).
Input: "Channel": number of channel to be configured
"DO" set the signal number which will set the output value.
Example VIs
SU7XX_XX_test.vi
