Difference between revisions of "Gate generator (GATEGEN)"
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= LogicPool (TEMPLATE) = | = LogicPool (TEMPLATE) = | ||
− | This module | + | This module will created a Pulse after the arrival of a trigger. The pulse width and delay can be set. After the pulse was created , the module can trigger it self again. This feature can be used to create CLOCKs. It Does not need any Hardware submodule to work. |
== Models == | == Models == | ||
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== LabVIEW Vi == | == LabVIEW Vi == | ||
− | === | + | === GATEGEN.vi === |
+ | |||
− | |||
[[File:GATEGENc.png]] | [[File:GATEGENc.png]] | ||
− | + | Pulse generator (GateGenerator) with programable Delay and Duration. Can be also used as Clock, Event or Time Counter. | |
The meaning of almost inputs and outputs of this Vi depends on the input "Function". The global inputs and outputs does not depend on the "function" input: | The meaning of almost inputs and outputs of this Vi depends on the input "Function". The global inputs and outputs does not depend on the "function" input: |
Revision as of 12:37, 3 May 2016
Contents
LogicPool (TEMPLATE)
This module will created a Pulse after the arrival of a trigger. The pulse width and delay can be set. After the pulse was created , the module can trigger it self again. This feature can be used to create CLOCKs. It Does not need any Hardware submodule to work.
Models
There is three model, the only diferent is the width of an internal counter.
Model 0 -> 32 Bits Model 1 -> 24 Bits Model 2 -> 16 Bits
Register Map
Module Address: 'G' or Ox47
Read register
Register Address | Name | Data |
---|---|---|
0 | VERSION, MODEL and Driver if any |
Bit 31..25: VERSION HI Bit 24..16: VERSION LOW Bit 15..8 : MODEL Bit 7: Status Bit 6..0: Driver |
1 | STATUS | Bit 7..0 is the counter active? is running? |
2 | COUNTER_VALUE | Bit 31..0 Counter value, the width depends on Model |
Write register
Register Address | Name | Data |
---|---|---|
0 | TRIGGER | Bit 7..0: Select the input driver of the trigger |
1 | ENABLE | Bit 7..0: Select the input driver of the enable signal of the counter |
2 | DELAY | Bit 31..0: Set the value of the delay after the trigger, after writing this register the counter will be reseted |
3 | DURATION | Bit 31..0: Set the width of the pulse, after writing this register the counter will be reseted |
4 | RETRIGGER | Bit 0: If set after the Pulse was created the counter will be reseted and the module will be triggered again. After writing this register the counter will be reseted |
LabVIEW Vi
GATEGEN.vi
Pulse generator (GateGenerator) with programable Delay and Duration. Can be also used as Clock, Event or Time Counter.
The meaning of almost inputs and outputs of this Vi depends on the input "Function". The global inputs and outputs does not depend on the "function" input:
Glogal Inputs
DIO_HV#: number of HV digital output to be accesed (1..255).
USB In: Handle to the LogicBox (create by open.vi), if not connected will take a global. parameter, this only works with one LogicBox at a time.
error in: error handling input
Global Outputs
USB out: Handle to the LogicBox.
error out: error handling output
Functions
Connect: enable, configurate and set input/value of the HV digital output. Inputs: "DO" : set the signal number which will drive the output, this signal can be set or clear manually using the module "B_S.vi" (Bool to Signal). "DI" : get the signal number of which drives this input.
Get Status: the cicuitry of the digital output can detect two errors, under voltage or logic state undifined. Only the first 8 channels support this features Input: "Channel": number of channel to be configured Output: Output Status
Set DO: set the signal number which will drive the output, this signal can be set or clear manually using the module "B_S.vi" (Bool to Signal). Input: "Channel": number of channel to be configured "DO" set the signal number which will set the output value.
Example VIs
SU7XX_XX_test.vi