Difference between revisions of "Gate generator (GATEGEN)"

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= LogicPool (TEMPLATE) =
 
= LogicPool (TEMPLATE) =
  
This module does not need any Hardware submodule to work.
+
This module will created a Pulse after the arrival of a trigger. The pulse width and delay can be set. After the pulse was created , the module can trigger it self again. This feature can be used to create CLOCKs. It Does not need any Hardware submodule to work.  
  
 
== Models ==
 
== Models ==
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Model 0 -> 32 Bits
 
Model 0 -> 32 Bits
 +
 
Model 1 -> 24 Bits
 
Model 1 -> 24 Bits
 +
 
Model 2 -> 16 Bits
 
Model 2 -> 16 Bits
 +
 +
Model 3 -> 32 Bits
 +
 +
Model 4 -> 24 Bits
 +
 +
Model 5 -> 16 Bits
 +
  
 
{{:CBUS_Address}}
 
{{:CBUS_Address}}
 
  
 
== Register Map ==
 
== Register Map ==
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! scope="col" | Data
 
! scope="col" | Data
 
|-
 
|-
| 0-9
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| 0
| Input Driver
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| TRIGGER
| Bit 7..0: Select the input driver of each output
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| Bit 7..0: Select the input driver of the trigger
|}
+
|-
 
+
| 1
=== Read/Write register ===
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| ENABLE
 
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| Bit 7..0: Select the input driver of the enable signal of the counter
{| border="1" class="wikitable"
 
|+ Read/Write registers
 
! scope="col" | Register Address
 
! scope="col" | Name
 
! scope="col" | Data
 
 
|-
 
|-
| 16
+
| 2
| CONFIG
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| DELAY
| Bit 9..0: output register
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| Bit 31..0: Set the value of the delay after the trigger, after writing this register the counter will be reseted, the width depends on Model
Bit 25..16: direct input mask
 
 
|-
 
|-
| 18
+
| 3
| Serial configuration
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| DURATION
| Serial Config, 15..8 C18..C11, 7..0 C08..C01
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| Bit 31..0: Set the width of the pulse, after writing this register the counter will be reseted, the width depends on Model
  Ignored if PUSHPL is high!
 
  C1_ C0_ O_ Config
 
  OLD 0  High-side mode, open-load detect=OLD
 
  X  1  Push-pull mode
 
 
|-
 
|-
|19
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| 4
|Parallel configuration
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| RETRIGGER
|
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| Bit 0: If a new trigger arrives and the gate ganerator is still runnig, abort the current pulse and generate a new pulse, if not set the trigger will be ignored. After writing this register the counter will be reseted
  Bit 3: PUSHPL - this is the global pin, if low, then can be set pin by pin using SPI
 
        high means the outputs 7..0 are push-pull, low - depending on the serial config
 
  Bit 2: unused
 
  Bit 1: SRIAL - low for parallel mode, hardwired now!
 
  Bit 0: global enable for outputs 7..0 (8..1)
 
 
|}
 
|}
  
 
== LabVIEW Vi ==
 
== LabVIEW Vi ==
  
=== TEMPLATE.vi ===
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=== GATEGEN.vi ===
  
Template VI for new designs
 
  
 +
[[File:GATEGENc.png]]
  
[[File:DO__HVc.png]]
 
  
Introduction.  
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Pulse generator (GateGenerator) with programable Delay and Duration.
  
 
The meaning of almost inputs and outputs of this Vi depends on the input "Function". The global inputs and outputs does not depend on the "function" input:
 
The meaning of almost inputs and outputs of this Vi depends on the input "Function". The global inputs and outputs does not depend on the "function" input:
Line 103: Line 95:
 
=== Glogal Inputs ===
 
=== Glogal Inputs ===
  
DIO_HV#: number of HV digital output to be accesed (1..255).
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GATEGEN#: number of gate generator to be accesed (1..255).
  
 
USB In: Handle to the LogicBox (create by open.vi), if not connected will take a global. parameter, this only works with one LogicBox at a time.
 
USB In: Handle to the LogicBox (create by open.vi), if not connected will take a global. parameter, this only works with one LogicBox at a time.
Line 118: Line 110:
  
  
   Connect: enable, configurate and set input/value of the HV digital output.
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   Connect: enable, configurate and set the trigger driver signal.
          Inputs:
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    Inputs:
          "DO: set the signal number which will drive the output, this signal can be set or clear
+
        "Params" set the Pulse delay and duration, width depends on model
                  manually using the module "B_S.vi" (Bool to Signal).
+
        "Enable" enable or disable the module
          "DI"  : get the signal number of which drives this input.  
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        "TRIG" set the signal number which will drive the trigger. This signal can be set or clear manually using the module "B_S.vi" (Bool to Signal).
       
+
        "Mode" Non retrigger: Ignore the trigger until the gate generator is free.
 +
                Retrigger: If a new trigger arrives and the gate ganerator is still runnig, abort the current pulse and generate a new pulse
 +
      Outputs:
 +
        "Gate" signal number in which the pulse is generated       
 +
 
 +
  Set Trig: set the signal number which will drive the trigger.
 +
    Input: "TRIG" set the signal number which will drive the trigger. This signal can be set or clear manually using the module "B_S.vi" (Bool to Signal).
 +
 
 +
  Set Enable: enable or disable the module
 +
    Input: "Enable" enable or disable the module
 +
   
 +
  Get Gate: get the gate (Pulse) value and the signal number in which the pulse is generated.
 +
    Output: "Gate" signal number in which the pulse is generated
 +
 
 +
  Read Busy: get the status of the module (Running or waiting for trigger)
 +
    Output: "Busy" status of the module
 +
 
 +
  Write Params: set the Pulse delay and duration.
 +
    Input: "Params" set the Pulse delay and duration, width depends on model
  
   Get Status: the cicuitry of the digital output can detect two errors, under voltage or logic state
+
   Read Counter: read the value of the internal counter used to generated the pulse:
              undifined. Only the first 8 channels support this features
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    Output: "Gate" contains the current value of the counter. 
              Input: "Channel": number of channel to be configured
 
              Output: Output Status
 
  
   Set DO: set the signal number which will drive the output, this signal can be set or clear manually
+
   Write Triggermode & Clear Counter: set Triggermode &  resets counter to 0.
          using the module "B_S.vi" (Bool to Signal).  
+
    Input: "Mode" Non retrigger: Ignore the trigger until the gate generator is free.
          Input: "Channel": number of channel to be configured
+
                  Retrigger: If a new trigger arrives and the gate ganerator is still runnig, abort the current pulse and generate a new pulse
                "DO" set the signal number which will set the output value.
 
  
 
=== Example VIs ===
 
=== Example VIs ===
  
SU7XX_XX_test.vi
+
LP_GateGen_Test.vi:

Latest revision as of 10:16, 10 May 2016

LogicPool (TEMPLATE)

This module will created a Pulse after the arrival of a trigger. The pulse width and delay can be set. After the pulse was created , the module can trigger it self again. This feature can be used to create CLOCKs. It Does not need any Hardware submodule to work.

Models

There is three model, the only diferent is the width of an internal counter.

Model 0 -> 32 Bits

Model 1 -> 24 Bits

Model 2 -> 16 Bits

Model 3 -> 32 Bits

Model 4 -> 24 Bits

Model 5 -> 16 Bits


CBUS Address

Register Map

Module Address: 'G' or Ox47

Read register

Read registers
Register Address Name Data
0 VERSION, MODEL and Driver if any
Bit 31..25: VERSION HI
Bit 24..16: VERSION LOW
Bit 15..8 : MODEL
Bit 7: Status
Bit 6..0: Driver
1 STATUS Bit 7..0 is the counter active? is running?
2 COUNTER_VALUE Bit 31..0 Counter value, the width depends on Model

Write register

Write registers
Register Address Name Data
0 TRIGGER Bit 7..0: Select the input driver of the trigger
1 ENABLE Bit 7..0: Select the input driver of the enable signal of the counter
2 DELAY Bit 31..0: Set the value of the delay after the trigger, after writing this register the counter will be reseted, the width depends on Model
3 DURATION Bit 31..0: Set the width of the pulse, after writing this register the counter will be reseted, the width depends on Model
4 RETRIGGER Bit 0: If a new trigger arrives and the gate ganerator is still runnig, abort the current pulse and generate a new pulse, if not set the trigger will be ignored. After writing this register the counter will be reseted

LabVIEW Vi

GATEGEN.vi

GATEGENc.png


Pulse generator (GateGenerator) with programable Delay and Duration.

The meaning of almost inputs and outputs of this Vi depends on the input "Function". The global inputs and outputs does not depend on the "function" input:

Glogal Inputs

GATEGEN#: number of gate generator to be accesed (1..255).

USB In: Handle to the LogicBox (create by open.vi), if not connected will take a global. parameter, this only works with one LogicBox at a time.

error in: error handling input

Global Outputs

USB out: Handle to the LogicBox.

error out: error handling output

Functions

 Connect: enable, configurate and set the trigger driver signal.
   Inputs:
        "Params" set the Pulse delay and duration, width depends on model
        "Enable" enable or disable the module 
        "TRIG" set the signal number which will drive the trigger. This signal can be set or clear manually using the module "B_S.vi" (Bool to Signal).
        "Mode" Non retrigger: Ignore the trigger until the gate generator is free.
               Retrigger: If a new trigger arrives and the gate ganerator is still runnig, abort the current pulse and generate a new pulse 
     Outputs:
        "Gate" signal number in which the pulse is generated         
 Set Trig: set the signal number which will drive the trigger.
   Input:  "TRIG" set the signal number which will drive the trigger. This signal can be set or clear manually using the module "B_S.vi" (Bool to Signal).
 Set Enable: enable or disable the module
   Input: "Enable" enable or disable the module 

 Get Gate: get the gate (Pulse) value and the signal number in which the pulse is generated.
   Output: "Gate" signal number in which the pulse is generated 
 Read Busy: get the status of the module (Running or waiting for trigger)
   Output: "Busy" status of the module
 Write Params: set the Pulse delay and duration.
   Input: "Params" set the Pulse delay and duration, width depends on model
 Read Counter: read the value of the internal counter used to generated the pulse:
   Output: "Gate" contains the current value of the counter.  
 Write Triggermode & Clear Counter: set Triggermode &  resets counter to 0.
   Input: "Mode" Non retrigger: Ignore the trigger until the gate generator is free.
                 Retrigger: If a new trigger arrives and the gate ganerator is still runnig, abort the current pulse and generate a new pulse

Example VIs

LP_GateGen_Test.vi: