Difference between revisions of "LogicPool"
(→LogicPool modules) |
|||
| (14 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
| + | = C++ = | ||
| + | [http://ew-dev.physi.uni-heidelberg.de/~rubio/LogicPoolCPP/index.html C++ online Documentation] | ||
| + | |||
| + | [http://physi.uni-heidelberg.de/~rubio/files/LogicBox/Docs/LogicPoolDocuCPP.zip C++ Documentation in zip file] | ||
| + | |||
| + | = LabVIEW = | ||
| + | |||
| + | == LogicPool modules == | ||
| + | |||
| + | [[Digital input/output (DIO)]] | ||
| + | |||
| + | [[Digital output high voltage (DO_HV)]] | ||
| + | |||
| + | [[Gate generator (GATEGEN)]] | ||
| + | |||
| + | [[Clock generator (CLOCK)]] | ||
| + | |||
| + | [[Counter (COUNTER)]] | ||
| − | |||
[[Charge to digital converter (QDC)]] | [[Charge to digital converter (QDC)]] | ||
| Line 9: | Line 26: | ||
[[Time to digital converter (TDC)]] | [[Time to digital converter (TDC)]] | ||
| − | |||
| − | |||
| Line 18: | Line 33: | ||
[[Pseudo-static RAM (PRAM)]] | [[Pseudo-static RAM (PRAM)]] | ||
| − | = Templates = | + | == Templates == |
[[SU7XX]] | [[SU7XX]] | ||
[[LP_module]] | [[LP_module]] | ||
| − | |||
| − | |||
| − | |||
| − | |||
Latest revision as of 10:15, 9 June 2016
Contents
C++
LabVIEW
LogicPool modules
Digital output high voltage (DO_HV)
Charge to digital converter (QDC)
Time to digital converter (TDC)
