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| | [[Firmware update (only DL706 and DL709)]] | | [[Firmware update (only DL706 and DL709)]] |
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| − | = LogicPool (QDC) =
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| − | This VHDL module needs a SU717 hardware sub-module to work.
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| − | == Register Map ==
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| − | → Read registers
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| − | {| style="border-spacing:0;"
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| − | | style="border-top:0.05pt solid #000000;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| '''Register address'''
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| − | | style="border-top:0.05pt solid #000000;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| '''Name'''
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| − | | style="border:0.05pt solid #000000;padding:0.097cm;"| '''Data'''
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| − | |-
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| '''0'''
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| OUT_BUS
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:0.05pt solid #000000;padding:0.097cm;"| Bit 7..0: Bus number that this module will drive
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| '''1'''
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| ADC(W)
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:0.05pt solid #000000;padding:0.097cm;"| Bit 15..0:
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| '''3'''
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| SPI
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:0.05pt solid #000000;padding:0.097cm;"|
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| − | |}
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| − | → Write registers
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| − | {| style="border-spacing:0;"
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| − | | style="border-top:0.05pt solid #000000;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| '''Register address'''
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| − | | style="border-top:0.05pt solid #000000;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| '''Register'''
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| − | '''Name'''
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| − | | style="border:0.05pt solid #000000;padding:0.097cm;"| '''Data'''
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| '''0'''
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| IN_TRIGGER
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:0.05pt solid #000000;padding:0.097cm;"| Bit 7..0: signal number to connect this module input
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| '''1'''
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| Gate(W)
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:0.05pt solid #000000;padding:0.097cm;"| Bit 15..0: gate width in 10 ns steps.
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| '''2'''
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| Control 1
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:0.05pt solid #000000;padding:0.097cm;"| Bit 7..0: Start delay
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| − | Bit 16..14: Mode
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| '''3'''
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| SPI
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:0.05pt solid #000000;padding:0.097cm;"|
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| '''4'''
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| Control 2
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| − | | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:0.05pt solid #000000;padding:0.097cm;"| Bit 7..0: Stop Delay
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| − | |}
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| − | == LabVIEW Vi ==
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| − | Gated Integrator with ADC and baseline correction.
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| − | Support: SU717
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| − | Inputs:
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| − | TRIGGER: Rising edge starts Gate for integration and data sampling.
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| − | Outputs:
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| − | BUS: Data & Strobe for ADC
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| − | PARAMS:
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| − | Gate/10ns: Length of Gate after Trigger in 10 ns
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| − | StartDelay: sampling point after start of GATE (incl. ADC-Pipeline=18)
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| − | StopDelay: sampling point after end of GATE (incl. ADC-Pipeline=18)
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| − | Mode:
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| − | normal: StopData-StartData will be recorded ( 15 bit signed!)
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| − | stop: Only StopData value recorded
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| − | start: Only StartData value recorded
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| − | start+stop: StartData & StopData values recorded
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| − | all: All ADC data values in gate recorded
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| − | Function:
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| − | Connect: connects in&outputs and loads all parameters.
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| − | Set TRIGGER: change input TRIGGER.
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| − | Get BUS: return Strobe
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| − | Write Params&Clear: loads parameters, clears FIFO
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| − | Read ADC: read data value
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| − | QDC#: number of module (must be unique)
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| − | USB In and USB Out are related to the selected USB interface!
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| − | No connection uses a global parameter, set by OPEN.vi!
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| − | '''''LabVIEW demos'''''
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| − | '''''Supported hardware'''''
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| − | [[SU717]]
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Introduction
The LogicBox is an electronic data adquisition und control system based on FPGA. It was developed at the "Physikalisches Institut Universität Heidelberg" to process and control typical Nuclear Physics experiments for scientific and educational purposes only.
The LogicBox consist of a FPGA main board with USB 1.1, USB-2 or VME interface and up to 8 I/O Sub-modules or extension cards with the necessary analogue or digital electronic to control or measure the desired signals. A firmware programmed into the FPGA as well as interface software allow the user to build fast and with flexibility a custom application.
The system can be found in 3 different chassis:
Base cards
| Format |
Product id |
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| Compact |
DL701 |
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| NIM |
DL706 or DL709 |
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| VME |
DL710 |
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The provided software is implemented in LabVIEW, This software library is called "LogicPool", and content a lot of soft-modules frequently used in the Nuclear Physics. The user can interconnect these modules, as he likes to create the desired setup.
We are working to improve the system with new sub-modules/extensions boards and faster interface to be able to process more data. At this moment we have developed 30 sub-modules as multiple coincidence, fan in / fan out, splitter, logic, discriminator, ADC, TDC, etc.,
The logicBox is the ideal replacement of the typical NIM racks with several non programmable NIM modules frequently used in the Nuclear Physics, which implement trigger Logic, rate meter, Time to digital converter, acquisition, etc.
Documentation
Base boards
Submodules (Extension boards)
LogicPool
German documentation
Old wikipage
Downloads
Logic Pool
PC Drivers
Firmware update (only DL706 and DL709)
