Difference between revisions of "LP module"
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=== Read/Write register === | === Read/Write register === | ||
| + | |||
| + | {| border="1" class="wikitable" | ||
| + | |+ Read/Write registers | ||
| + | ! scope="col" | Register Address | ||
| + | ! scope="col" | Name | ||
| + | ! scope="col" | Data | ||
| + | |- | ||
| + | | 0 | ||
| + | | MUX_IN | ||
| + | | Bit 7..0: multiplexer address | ||
| + | |- | ||
| + | | 1 | ||
| + | | STATE_IN | ||
| + | | Bit 7..0: input value | ||
| + | |} | ||
== LabVIEW Vi == | == LabVIEW Vi == | ||
Revision as of 08:14, 25 February 2014
Contents
LogicPool (QDC)
A brief introduction: This VHDL module needs a SU7XX hardware sub-module to work.... This module is software implementation, no need of hardware to work.....
Models
There is only one model for this module.
Supported Hardware
SU7XX Just a link to the hardware module if any
Register Map
Read register
Module Address: 'T' or Ox??
| Register Address | Name | Data |
|---|---|---|
| 0 | MUX_IN | Bit 7..0: multiplexer address |
| 1 | STATE_IN | Bit 7..0: input value |
Write register
| Register Address | Name | Data |
|---|---|---|
| 0 | MUX_OUT | Bit 7..0: multiplexer address |
| 1 | Debounce | Bit 7..0: input value |
| 2 | Mode | Bit 0:
'1' 50 Ohm termination '0' Open Bit 1: NIM/TTL '1' NIM '0' TTL |
Read/Write register
| Register Address | Name | Data |
|---|---|---|
| 0 | MUX_IN | Bit 7..0: multiplexer address |
| 1 | STATE_IN | Bit 7..0: input value |
