Difference between revisions of "Charge to digital converter (QDC)"
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== Supported Hardware == | == Supported Hardware == | ||
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== Register Map == | == Register Map == | ||
Latest revision as of 08:37, 25 February 2014
Contents
LogicPool (QDC)
This VHDL module needs a SU717 hardware sub-module to work.
Models
There is only one model for this module.
Supported Hardware
Register Map
Module Address: 'Q' or Ox??
Read register
| Register Address | Name | Data |
|---|---|---|
| 0 | OUT_BUS | Bit 7..0: Bus number that this module drives, through this bus the ADC value (raw or processed, see mode) can be saved in a LogicPool FIFO. |
| 1 | ADC(W) | Bit 15..0: Register with the last ADC value (raw or processed, see mode) |
Write register
| Register Address | Name | Data |
|---|---|---|
| 0 | IN_TRIGGER | Bit 7..0: signal number to connect this module input. The module must be triggered to start an acquisition. |
| 1 | Gate(W) | Bit 15..0: gate width in 10 ns steps. Integration time in 10 ns steps |
| 2 | Control 1 | Bit 7..0: Start delay: sampling point after the trigger arrives and the integration time has been started.
Bit 16..14: Mode: “000” The difference between the start acquisition point and stop will be calculated.
Data format is 15-Bit signed.
“001” Only the stop point will be readout.
“010” Only the start point will be readout.
“011” The start and stop point will be readout.
“100” All ADC values from start to stop will be readout. This mode is the best way
to determinate the start and stop sample time.
|
| 4 | Control 2 | Bit 7..0: Stop Delay: sampling point after the integration time has been finished. |
| 5 | Clock control | The ADC parallel data will be readout synchronized with the FPGA clock, in order to sample the data
in the stable state the user can shift the clock phase in 256 steps from 0 to 10 ns. '1' increments the clock phase in one step. '0' decrements the clock phase in one step. |
LabVIEW Vi
Gated Integrator with ADC and baseline correction. Support: SU717
Inputs
QDC#: number of module (must be unique) USB In and USB Out are related to the selected USB interface! No connection uses a global parameter, set by OPEN.vi! TRIGGER: Rising edge starts Gate for integration and data sampling.
Outputs
BUS: Data & Strobe for ADC
Parameters
Gate/10ns: Length of Gate after Trigger in 10 ns StartDelay: sampling point after start of GATE (incl. ADC-Pipeline=18) StopDelay: sampling point after end of GATE (incl. ADC-Pipeline=18) Mode: normal: StopData-StartData will be recorded ( 15 bit signed!) stop: Only StopData value recorded start: Only StartData value recorded start+stop: StartData & StopData values recorded all: All ADC data values from start to stop are recorded
Functions
Connect: connects in&outputs and loads all parameters. Set TRIGGER: change input TRIGGER. Get BUS: return Strobe Write Params&Clear: loads parameters, clears FIFO Read ADC: read data value
Demo software
SU717_QDC.vi
