SU741

SU741 pin table (direction shown for the SU board!)

 power    in            +5V  2    1 +5V             in     power
 LVTTL bidir           D<1>  4    3 D<0>            bidir  LVTTL
 LVTTL bidir           D<3>  6    5 D<2>            bidir  LVTTL
 LVTTL bidir           D<5>  8    7 D<4>            bidir  LVTTL
 LVTTL bidir           D<7> 10    9 D<6>            bidir  LVTTL
 LVTTL bidir           D<9> 12   11 D<8>            bidir  LVTTL
 LVTTL bidir          D<11> 14   13 D<10>           bidir  LVTTL
 LVTTL bidir          D<13> 16   15 D<12>           bidir  LVTTL
 LVTTL bidir          D<15> 18   17 D<14>           bidir  LVTTL
 LVTTL    in            REQ 20   19 READ_n          in     LVTTL
 LVTTL    in        Addr<1> 22   21 Addr<0>         in     LVTTL
 LVTTL    in          CMD_n 24   23 Sync            in     LVTTL
 LVTTL   out          READY 26   25 CLK             in     LVTTL
 LVTTL    in            DAC 28   27 FCLR            in     LVTTL
    *     in          LDACn 30   29 SPI_SDO_CLR     out    *
    *     in        SPI_CLK 32   31 SPI_DIN2        in     *
    *     in       SPI_DIN1 34   33 SPI_Sync_n      in     *
 power    in            GND 36   35 GND             in     power

• Note: when FCLR is 1, the DAC and SPI signals (pin29..pin34) can be driven from the LogicBox.

Otherwise the LogicBox should NOT drive these 6 signals! They are driven by the FPGA on SU741!

Differences to SU730 as till Feb 2014:

- the memory is 4M x 16 instead of 8M x 16

- there is a direct connection to the SPI and DAC interface

- no HISTO and CRE signals on the SU-connector (CRE was anyway not used)

- Addr2 is now Sync (10 MHz for time measurement), therefore 2 instead of 4 address pointers

- DAC signal has another meaning (was anyway not used before)

- control/command/status registers - still not fully defined and implemented, used for start/pause/stop and more.

Interface:

req cmd_n   iaddr1    iaddr0 read_n dac fclr Bits  Name   Comment
x   x       x         x      x      x   1    x     -      clear address counters and state machines, tri-state the SPI signals
1   0       N=0..1    0      1      0   0    16    AC0..1 write bits 15.. 0 of address counter N, AC[N][15..0]=DI
1   0       N=0..1    1      1      0   0     6    AC0..1 write bits 21..16 of address counter N, AC[N][21..16]=DI[5..0]
1   0       N=0..1    0      0      0   0    16    AC0..1 read lower part of address counter: DO=AC[N][15..0]
1   0       N=0..1    1      0      0   0     6    AC0..1 read upper part of address counter: DO[5..0]=AC[N][21..16]
----------------------------------------------------------
1   0         N=0..3         1      1   0    16    CR0..3 write control/command register CR[N]
1   0         N=0..3         0      1   0    16    CR0..3 read control/command/status register CR[N]
----------------------------------------------------------
1   1       N=0..1    0      1      0   0    16           memory write: mem[AC[N]]=DI
1   1       N=0..1    1      1      0   0    16           memory write with address increment: mem[AC[N]]=DI, AC[N]++
----------------------------------------------------------
1   1       N=0..1    0      0      0   0    16           memory read: DO=mem[AC[N]]
1   1       N=0..1    1      0      0   0    16           memory read with address increment: DO=mem[AC[N]], AC[N]++
----------------------------------------------------------
---------------------------------------------------------------------

 DI are the data coming from the Logic Box
 DO are the data to the Logic Box

 sync is a slow clock (10 MHz) for the time measurement

 Bit positions                       writing to CR[0] : 0 : start from the beginning, 1 : pause, 2 : stop ...
 DI/DO   0..15
 read_n  16
 req     17
 iaddr   18..19
 sync    20
 cmd_n   21
 clk     22
 ready   23
 fclr    24
 dac     25

How to operate:

1) init the address both pointers with the same (either with fclr or by writing to AC[0] and AC[1])

2) write the memory content with address autoincrement using e.g. AC[1]

3) start the sequency by writing to the CR[0] (to be defined in details)

4) later reading status from CR is allowed, but memory read/write is blocked while running the sequence