SU730

Description

channel up to 16-bit isolated DAC and integrated PSRAM 8M x 16 bit

Pinout

SU730 pin table (direction shown for the SU board!)

 power    in            +5V  2    1 +5V             in     power
 LVTTL bidir     SDO_1/D<1>  4    3 D<0>/SDO_0      bidir  LVTTL
 LVTTL bidir   SPI_CSn/D<3>  6    5 D<2>/SCLK       bidir  LVTTL
 LVTTL bidir           D<5>  8    7 D<4>            bidir  LVTTL
 LVTTL bidir           D<7> 10    9 D<6>            bidir  LVTTL
 LVTTL bidir           D<9> 12   11 D<8>            bidir  LVTTL
 LVTTL bidir          D<11> 14   13 D<10>           bidir  LVTTL
 LVTTL bidir          D<13> 16   15 D<12>           bidir  LVTTL
 LVTTL bidir          D<15> 18   17 D<14>           bidir  LVTTL
 LVTTL    in            REQ 20   19 READ_n          in     LVTTL
 LVTTL    in        Addr<1> 22   21 Addr<0>         in     LVTTL
 LVTTL    in          CMD_n 24   23 Addr<2>/SYNC    in     LVTTL
 LVTTL   out          READY 26   25 CLK             in     LVTTL
 LVTTL    in            DAC 28   27 FCLR            in     LVTTL
 LVTTL    in        -/HISTO 30   29 CRE/-           in     LVTTL
    NC     -              - 32   31 -               -      NC
    NC     -              - 34   33 -               -      NC
 power    in            GND 36   35 GND             in     power

Memory & Histogramming FPGA design:

req cmd_n iaddr2..1 iaddr0 read_n hist dac fclr Bits  Name   Comment
x   x     x         x      x      x    x   1    x     -      clear address counters, used in fifo mode
1   0     N=0..3    0      1      0    0   0    16    AC0..3 write bits 15.. 0 of address counter N, AC[N][15..0]=DI
1   0     N=0..3    1      1      0    0   0     7    AC0..3 write bits 22..16 of address counter N, AC[N][22..16]=DI[6..0]
1   0     N=0..3    0      0      0    0   0    16    AC0..3 read lower part of address counter: DO=AC[N][15..0]
1   0     N=0..3    1      0      0    0   0     7    AC0..3 read upper part of address counter: DO[6..0]=AC[N][22..16]
-------------------------------------------------------------
1   0     N=0..3    0      1      1    0   0    7-16  PG0..3 write page # for histogramming, PG[N]=DI
1   0     N=0..3    1      1      1    0   0     4    HS0..3 write # of bits in the histogram, HS[N]=DI
1   0     N=0..3    0      0      1    0   0    7-16  PG0..3 read page # for histogramming: DO=PG[N]
1   0     N=0..3    1      0      1    0   0     4    HS0..3 read # of bits in the histogram: DO=HS[N]
-------------------------------------------------------------Version = Bits 15..8 when reading HS[i] or upper part of AC[i]
1   0     N=0..3    i      1      0    1   0    16    DAC0.1 write to the DAC[N & 1]=DI, if i=1 send to DACs serially
1   0     N=0..3    i      0      0    1   0    16    DAC0.1 read DAC[N & 1], if i=1 send to DACs serially
-------------------------------------------------------------
1   1     N=0..3    0      1      0    0   0    16           memory write: mem[AC[N]]=DI
1   1     N=0..3    1      1      0    0   0    16           memory write with address increment: mem[AC[N]]=DI, AC[N]++
-------------------------------------------------------------
1   1     N=0..3    0      0      h    d   0    16           memory read: DO=mem[AC[N]]
1   1     N=0..3    1      0      h    d   0    16           memory read with address increment: DO=mem[AC[N]], AC[N]++
                                                             In both cases 1) if h=0 DAC[N & 1]=DO; 2) if d=1 send serially
-------------------------------------------------------------
1   1     N=0..3    x      1      1    0   0    16           read +1 write: mem[PA(N,DI)]++, if 0 mem[PA(N,DI)+1]++
-------------------------------------------------------------
PA(N,DI) = ( (PG[N] << (HS[N]+1) ) + (DI & (Bins[N]-1)) ) << 1 when DI < Bins[N], else = last bin of the page
--------------------------------------------------------------------------------------------------------
Possible combinations:                                 |   DI are the data coming from the Logic Box
HS     Bins    PG          max # pages                 |   DO are the data to the Logic Box
0..4   --------- invalid! ------                       |
 5       64    0..0xFFFF   65536                       |   Bit positions
 6      128    0..0x7FFF   32768                       |   DI/DO   0..15
 7      256    0..0x3FFF   16384                       |   read_n  16
 8      512    0..0x1FFF    8192                       |   req     17
 9     1024    0..0x0FFF    4096                       |   iaddr   18..20
10     2048    0..0x07FF    2048                       |   cmd_n   21
11     4096    0..0x03FF    1024                       |   clk     22
12     8192    0..0x01FF     512                       |   fclr    24
13    16384    0..0x00FF     256                       |   dac     25
14    32768    0..0x007F     128                       |   cre     26  - not implemented, should be low
15    65536    0..0x003F      64                       |   hist    27

DAC FPGA design (compatible to SU741):

- only the differences:

• D0..D3 are SPI signals (inputs) when FCLR=1, so the LogicBox main board can directly access the two DACs.
• HISTO and CRE are not used, histogramming mode is not available
• Addr<2> is SYNC, a clock used for the time measurement, typically 10 or 100 MHz.

- compared to SU741 the differences are

• the position of the SPI signals (when driven from the SU-Connector(LogicBox))
• the memory size (8 M x 16) is twice the memory on SU741 (4 M x 16)
• two DACs (SU730) instead of 8 (SU741)
• no initialisation of the two DACs (necessary for SU741)