Difference between revisions of "SU701"
(Created page with "SU701 pin table (direction shown for the SU board!) power in +5V 2 1 +5V in power LVTTL in DIR_A 4 3 OE_A_n in ...") |
|||
| (6 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
| + | = Description = | ||
| + | |||
| + | This module has 16 independent 5.0V TTL input/output (configured through a jumper), this IOs are routed to a pin row connector. The signals are divided into two groups of 8 DIOs, so the user can configure one group as input or ouput through a FPGA register. | ||
| + | The used IC is the 74FCT164245T. There is no pull-down or pull-up resistors. The submodule contains 8 LEDs too, witch are direct connected to FPGA outputs, the LEDs can be configured through internal registers. | ||
| + | |||
| + | = Block Diagram = | ||
| + | |||
| + | [[File:SU701_block_diagram.png]] | ||
| + | |||
| + | |||
| + | = Front panel = | ||
| + | |||
| + | [[File:SU701_front_panel.png]] | ||
| + | |||
| + | = Back Connector = | ||
| + | |||
SU701 pin table (direction shown for the SU board!) | SU701 pin table (direction shown for the SU board!) | ||
| Line 19: | Line 35: | ||
NC - - 34 33 - - NC | NC - - 34 33 - - NC | ||
power in GND 36 35 GND in power | power in GND 36 35 GND in power | ||
| + | |||
| + | = Power consumption = | ||
| + | |||
| + | == Version 0 == | ||
| + | |||
| + | +5V -> XX mA | ||
| + | -5V -> XX mA | ||
| + | |||
| + | = Measurement = | ||
| + | |||
| + | == Version 0 == | ||
| + | |||
| + | = Compatibility = | ||
| + | |||
| + | This module is compatible with all base boards | ||
Latest revision as of 16:00, 8 September 2014
Contents
Description
This module has 16 independent 5.0V TTL input/output (configured through a jumper), this IOs are routed to a pin row connector. The signals are divided into two groups of 8 DIOs, so the user can configure one group as input or ouput through a FPGA register. The used IC is the 74FCT164245T. There is no pull-down or pull-up resistors. The submodule contains 8 LEDs too, witch are direct connected to FPGA outputs, the LEDs can be configured through internal registers.
Block Diagram
Front panel
Back Connector
SU701 pin table (direction shown for the SU board!)
power in +5V 2 1 +5V in power
LVTTL in DIR_A 4 3 OE_A_n in LVTTL
LVTTL bidir A<1> 6 5 A<2> bidir LVTTL
LVTTL bidir A<3> 8 7 A<4> bidir LVTTL
LVTTL bidir A<5> 10 9 A<6> bidir LVTTL
LVTTL bidir A<7> 12 11 A<8> bidir LVTTL
LVTTL bidir B<1> 14 13 B<2> bidir LVTTL
LVTTL bidir B<3> 16 15 B<4> bidir LVTTL
LVTTL bidir B<5> 18 17 B<6> bidir LVTTL
LVTTL bidir B<7> 20 19 B<8> bidir LVTTL
LVTTL in OE_B_n 22 21 DIR_B in LVTTL
LVTTL in LED_n<1> 24 23 LED_n<2> in LVTTL
LVTTL in LED_n<3> 26 25 LED_n<4> in LVTTL
LVTTL in LED_n<5> 28 27 LED_n<6> in LVTTL
LVTTL in LED_n<7> 30 29 LED_n<8> in LVTTL
NC - - 32 31 - - NC
NC - - 34 33 - - NC
power in GND 36 35 GND in power
Power consumption
Version 0
+5V -> XX mA -5V -> XX mA
Measurement
Version 0
Compatibility
This module is compatible with all base boards
