Difference between revisions of "Time to digital converter (TDC)"
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| − | + | This module is a software implementation, no need of hardware to work. The TDC will capture the time stamp of the input channels by rising edge so long the gate is activated. The maximal time resolution is 10 ns and can be changed through a programmable register, an external signal can be used as TDC clock too. | |
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== Models == | == Models == | ||
Revision as of 14:45, 27 January 2015
Contents
LogicPool (TDC)
This module is a software implementation, no need of hardware to work. The TDC will capture the time stamp of the input channels by rising edge so long the gate is activated. The maximal time resolution is 10 ns and can be changed through a programmable register, an external signal can be used as TDC clock too.
Models
There is only one model for this module.
Supported Hardware
SU7XX Just a link to the hardware module if any
Register Map
Module Address: 'T' or Ox??
Read register
| Register Address | Name | Data |
|---|---|---|
| 0 | MUX_IN | Bit 7..0: multiplexer address |
| 1 | STATE_IN | Bit 7..0: input value |
Write register
| Register Address | Name | Data |
|---|---|---|
| 0 | MUX_OUT | Bit 7..0: multiplexer address |
| 1 | Debounce | Bit 7..0: input value |
| 2 | Mode | Bit 0:
'1' 50 Ohm termination '0' Open Bit 1: NIM/TTL '1' NIM '0' TTL |
Read/Write register
| Register Address | Name | Data |
|---|---|---|
| 0 | MUX_IN | Bit 7..0: multiplexer address |
| 1 | STATE_IN | Bit 7..0: input value |
LabVIEW Vi
Inputs
Input 1: Input 2:
Outputs
Output 1: Output 2:
Parameters
Param 1: Param 2:
Functions
Function 1: Function 2:
