Difference between revisions of "LogicPool"
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| + | = C++ = | ||
| + | [http://ew-dev.physi.uni-heidelberg.de/~rubio/LogicPoolCPP/index.html C++ online Documentation] | ||
| + | |||
| + | [http://physi.uni-heidelberg.de/~rubio/files/LogicBox/Docs/LogicPoolDocuCPP.zip C++ Documentation in zip file] | ||
| + | |||
| + | = LabVIEW = | ||
| + | |||
| + | == LogicPool modules == | ||
| + | |||
| + | [[Digital input/output (DIO)]] | ||
| + | |||
| + | [[Digital output high voltage (DO_HV)]] | ||
| + | |||
| + | [[Gate generator (GATEGEN)]] | ||
| + | |||
| + | [[Clock generator (CLOCK)]] | ||
| + | |||
| + | [[Counter (COUNTER)]] | ||
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[[Discriminator]] | [[Discriminator]] | ||
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[[Pseudo-static RAM (PRAM)]] | [[Pseudo-static RAM (PRAM)]] | ||
| − | = Templates = | + | == Templates == |
[[SU7XX]] | [[SU7XX]] | ||
[[LP_module]] | [[LP_module]] | ||
Latest revision as of 10:15, 9 June 2016
Contents
C++
LabVIEW
LogicPool modules
Digital output high voltage (DO_HV)
Charge to digital converter (QDC)
Time to digital converter (TDC)
