Difference between revisions of "LP module"

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(→‎LogicPool (QDC))
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= LogicPool (QDC) =
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= LogicPool (DIO) =
  
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A brief introduction: This VHDL module needs a SU7XX hardware sub-module to work....
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This VHDL module needs a SU7XX hardware sub-module to work.
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This module is software implementation, no need of hardware to work.....
 
  
 
== Models ==
 
== Models ==
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== Supported Hardware ==
 
== Supported Hardware ==
  
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[[SU7XX]] Just a link to the hardware module if any
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[[SU7XX]]
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== Register Map ==
 
== Register Map ==
  
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Module Address: 'T' or Ox??
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Module Address: 'C' or OxFF
  
 
=== Read register ===
 
=== Read register ===
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|-
 
|-
 
| 0
 
| 0
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| MUX_IN
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| VERSION AND MODEL
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| Bit 7..0: multiplexer address
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| Bit 7..0:  
 
|-
 
|-
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| 1
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| 17
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| STATE_IN
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| Status
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| Bit 7..0: input value
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| MAX14900E status, 15..8 F8..F1, 7..0 S8..1
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  F_ S_ O_ Status
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  0  s  No fault detected, logic state of O_ is s
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  1  0  Fault detected, logic state not defined
 +
  1  1  Under voltage lockout detected
 
|}
 
|}
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=== Write register ===
 
=== Write register ===
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! scope="col" | Data
 
! scope="col" | Data
 
|-
 
|-
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|0  
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| 0-9
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|MUX_OUT
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| Input Driver
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|Bit 7..0: multiplexer address
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| Bit 7..0: Select the input driver of each output
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|-
 
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|1
 
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|Debounce
 
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|Bit 7..0: input value
 
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|-
 
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|2
 
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| Mode
 
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|Bit 0:
 
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'1' 50 Ohm termination
 
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'0' Open
 
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Bit 1: NIM/TTL
 
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'1' NIM
 
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'0' TTL 
 
 
|}
 
|}
  
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! scope="col" | Data
 
! scope="col" | Data
 
|-
 
|-
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| 0
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| 16
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| MUX_IN
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| CONFIG
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| Bit 7..0: multiplexer address
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| Bit 9..0: output register
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Bit 25..16: direct input mask
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|-
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| 18
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| Serial configuration
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| Serial Config, 15..8 C18..C11, 7..0 C08..C01
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  Ignored if PUSHPL is high!
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  C1_ C0_ O_ Config
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  OLD 0  High-side mode, open-load detect=OLD
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  X  1  Push-pull mode
 
|-
 
|-
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| 1
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|19
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| STATE_IN
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|Parallel configuration
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| Bit 7..0: input value
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|
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  Bit 3: PUSHPL - this is the global pin, if low, then can be set pin by pin using SPI
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        high means the outputs 7..0 are push-pull, low - depending on the serial config
 +
  Bit 2: unused
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  Bit 1: SRIAL - low for parallel mode, hardwired now!
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  Bit 0: global enable for outputs 7..0 (8..1)
 
|}
 
|}
  
 
== LabVIEW Vi ==
 
== LabVIEW Vi ==
  
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=== Inputs ===
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=== DO_HV.vi ===
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High voltage digital output
  
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  Input 1:
 
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  Input 2:
 
  
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[[File:DO__HVc.png]]
  
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=== Outputs ===
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This Vi controls one high voltage digital output. The meaning of almost inputs and outputs of this Vi depends on the input "Function". The global inputs and outputs does not depend on the "function" input:
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  Output 1:
 
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  Output 2:
 
  
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=== Parameters ===
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=== Glogal Inputs ===
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  Param 1:  
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  Param 2:
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DIO_HV#: number of HV digital output to be accesed (1..255).
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 +
USB In: Handle to the LogicBox (create by open.vi), if not connected will take a global. parameter, this only works with one LogicBox at a time.
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 +
error in: error handling input
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=== Global Outputs ===
 +
 
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USB out: Handle to the LogicBox.
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 +
error out: error handling output
  
 
=== Functions ===
 
=== Functions ===
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  Function 1:
 
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  Function 2:
 
  
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=== Demo software ===
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  Connect: enable, configurate and set input/value of the HV digital output.
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          Inputs:
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          "Channel": number of channel to be configured
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          "DO" set the signal number which will set the output value.
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          "Enable" enable or disable the output of all first 8 channels.
 +
          "Mode" set the output as Push pull or High Side
 +
       
 +
 
 +
  Get Status: the cicuitry of the digital output can detect two errors, under voltage or logic state
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              undifined. Only the first 8 channels support this features
 +
              Input: "Channel": number of channel to be configured
 +
              Output: Output Status
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 +
  Set DO: set the signal number which will drive the output, this signal can be set or clear manually
 +
          using the module "B_S.vi" (Bool to Signal).
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          Input: "Channel": number of channel to be configured
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                "DO" set the signal number which will set the output value.
 +
 
 +
 
 +
=== Example VIs ===
 +
 
 +
SU7XX_XX_test.vi

Revision as of 11:23, 3 May 2016

LogicPool (DIO)

This VHDL module needs a SU7XX hardware sub-module to work.

Models

There is only one model for this module.

CBUS Address


Supported Hardware

SU7XX

Register Map

Module Address: 'C' or OxFF

Read register

Read registers
Register Address Name Data
0 VERSION AND MODEL Bit 7..0:
17 Status MAX14900E status, 15..8 F8..F1, 7..0 S8..1 
 F_ S_ O_ Status
 0  s  No fault detected, logic state of O_ is s
 1  0  Fault detected, logic state not defined
 1  1  Under voltage lockout detected

Write register

Write registers
Register Address Name Data
0-9 Input Driver Bit 7..0: Select the input driver of each output

Read/Write register

Read/Write registers
Register Address Name Data
16 CONFIG Bit 9..0: output register

Bit 25..16: direct input mask

18 Serial configuration Serial Config, 15..8 C18..C11, 7..0 C08..C01 
 Ignored if PUSHPL is high!
 C1_ C0_ O_ Config
 OLD 0   High-side mode, open-load detect=OLD
 X   1   Push-pull mode
19 Parallel configuration 
 Bit 3: PUSHPL - this is the global pin, if low, then can be set pin by pin using SPI
        high means the outputs 7..0 are push-pull, low - depending on the serial config
 Bit 2: unused
 Bit 1: SRIAL - low for parallel mode, hardwired now!
 Bit 0: global enable for outputs 7..0 (8..1)

LabVIEW Vi

DO_HV.vi

High voltage digital output


DO HVc.png

This Vi controls one high voltage digital output. The meaning of almost inputs and outputs of this Vi depends on the input "Function". The global inputs and outputs does not depend on the "function" input:

Glogal Inputs

DIO_HV#: number of HV digital output to be accesed (1..255).

USB In: Handle to the LogicBox (create by open.vi), if not connected will take a global. parameter, this only works with one LogicBox at a time.

error in: error handling input

Global Outputs

USB out: Handle to the LogicBox.

error out: error handling output

Functions

 Connect: enable, configurate and set input/value of the HV digital output.
          Inputs:
          "Channel": number of channel to be configured 
          "DO" set the signal number which will set the output value.
          "Enable" enable or disable the output of all first 8 channels.
          "Mode" set the output as Push pull or High Side
       

 Get Status: the cicuitry of the digital output can detect two errors, under voltage or logic state
             undifined. Only the first 8 channels support this features
             Input: "Channel": number of channel to be configured 
             Output: Output Status

 Set DO: set the signal number which will drive the output, this signal can be set or clear manually
         using the module "B_S.vi" (Bool to Signal). 
         Input: "Channel": number of channel to be configured
                "DO" set the signal number which will set the output value.


Example VIs

SU7XX_XX_test.vi

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