Difference between revisions of "Charge to digital converter (QDC)"
(Created page with "= LogicPool (QDC) = This VHDL module needs a SU717 hardware sub-module to work. == Models == There is only one model for this module. {{:CBUS_Address}} == Supported Har...") |
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|The ADC parallel data will be readout synchronized with the FPGA clock, in order to sample the data in the stable state the user can shift the clock phase in 256 steps from 0 to 10 ns. | |The ADC parallel data will be readout synchronized with the FPGA clock, in order to sample the data in the stable state the user can shift the clock phase in 256 steps from 0 to 10 ns. | ||
| − | '1' increments the clock phase in one step. | + | '1' increments the clock phase in one step. |
| − | '0' decrements the clock phase in one step. | + | '0' decrements the clock phase in one step. |
|} | |} | ||
Revision as of 08:33, 25 February 2014
Contents
LogicPool (QDC)
This VHDL module needs a SU717 hardware sub-module to work.
Models
There is only one model for this module.
Supported Hardware
SU7XX Just a link to the hardware module if any
Register Map
Module Address: 'Q' or Ox??
Read register
| Register Address | Name | Data |
|---|---|---|
| 0 | OUT_BUS | Bit 7..0: Bus number that this module drives, through this bus the ADC value (raw or processed, see mode) can be saved in a LogicPool FIFO. |
| 1 | ADC(W) | Bit 15..0: Register with the last ADC value (raw or processed, see mode) |
Write register
| Register Address | Name | Data |
|---|---|---|
| 0 | IN_TRIGGER | Bit 7..0: signal number to connect this module input. The module must be triggered to start an acquisition. |
| 1 | Gate(W) | Bit 15..0: gate width in 10 ns steps. Integration time in 10 ns steps |
| 2 | Control 1 | Bit 7..0: Start delay: sampling point after the trigger arrives and the integration time has been started.
Bit 16..14: Mode: “000” The difference between the start acquisition point and stop will be calculated. Data format is 15-Bit signed. “001” Only the stop point will be readout. “010” Only the start point will be readout. “011” The start and stop point will be readout. “100” All ADC values from start to stop will be readout. This mode is the best way to determinate the start and stop sample time. |
| 4 | Control 2 | Bit 7..0: Stop Delay: sampling point after the integration time has been finished. |
| 5 | Clock control | The ADC parallel data will be readout synchronized with the FPGA clock, in order to sample the data in the stable state the user can shift the clock phase in 256 steps from 0 to 10 ns.
'1' increments the clock phase in one step. '0' decrements the clock phase in one step. |
Read/Write register
| Register Address | Name | Data |
|---|---|---|
| 0 | MUX_IN | Bit 7..0: multiplexer address |
| 1 | STATE_IN | Bit 7..0: input value |
LabVIEW Vi
Inputs
Input 1: Input 2:
Outputs
Output 1: Output 2:
Parameters
Param 1: Param 2:
Functions
Function 1: Function 2:
