Difference between revisions of "SU750"
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* EVNT_SIZE (3 bits) at 1 | * EVNT_SIZE (3 bits) at 1 | ||
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evnt_size Event Size[samples] | evnt_size Event Size[samples] | ||
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110 1024 | 110 1024 | ||
111 1024 (later 2048) | 111 1024 (later 2048) | ||
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| + | * LED (5 bits) at 2 | ||
| + | |||
| + | * SEND_TP (2 bits) at 3 | ||
| + | |||
| + | Bit 1 : when 0 => normal ADC data else testpattern data | ||
| + | Bit 0 : when 0 => 0x3FFF -> 0x0000 else 0x2AAA -> 0x1555 | ||
Revision as of 14:16, 2 December 2014
SU750 pin table (direction shown for the SU board!)
power in +5V 2 1 +5V in power LVTTL bidir SDA 4 3 SCL in LVTTL LVTTL out DATA<1> 6 5 DATA<0> out LVTTL LVTTL out DATA<3> 8 7 DATA<2> out LVTTL LVTTL out DATA<5> 10 9 DATA<4> out LVTTL LVTTL out DATA<7> 12 11 DATA<6> out LVTTL LVTTL out DATA<9> 14 13 DATA<8> out LVTTL LVTTL out DATA<11> 16 15 DATA<10> out LVTTL LVTTL out DATA<13> 18 17 DATA<12> out LVTTL LVTTL in TRIGG 20 19 VALID out LVTTL LVTTL in FREQ<2> 22 21 SPI_CONF in LVTTL LVTTL in FREQ<1> 24 23 FREQ<0> in LVTTL LVTTL in RESET 26 25 CLK_READ in LVTTL LVTTL out SDRD 28 27 SEn in LVTTL LVTTL in SCLKn 30 29 SDATA in LVTTL LVTTL out PGND<1> 32 31 PGND<0> out LVTTL LVTTL in CLKp 34 33 CLKn in LVTTL power in GND 36 35 GND in power
Differences to SU735:
- Pinout
SU735 SU750 PIN GI_GATE (in) VALID (out) 19 SPARE<1> TRIGG (in) 20 SPARE<2> SPI_CONF (in) 21 SPARE<3> FREQ<2> (in) 22 (still not used in design) CLK_CPU CLK_READ 25 (was not used in the latest firmware of SU735) - GND 31, 32
- SU750 should get ALWAYS 100 MHz at CLKp and CLKn!
- CLK_READ can be 100 MHz or below, it is used to clock out the data from the internal memory
- VALID = 1 means valid output data
- TRIGG = 1 starts the data storing, shortly after triggering the readout is started as a complete block, with VALID=1 indicatiing valid data.
- SPI_CONF = 1 selects the internal configuration registers instead of the ADC (and disconnects the ADC SPI).
The SPI Word has 16 bits (like of the ADC), the upper 3 (MSB) bits are address, the next bit is read(0) or write(1), the other 12 (LSB) bits are data.
SPI configuration registers:
- PRESAMPLE (10 bits) at 0
- EVNT_SIZE (3 bits) at 1
evnt_size Event Size[samples] 000 16 001 32 010 64 011 128 100 256 101 512 110 1024 111 1024 (later 2048)
- LED (5 bits) at 2
- SEND_TP (2 bits) at 3
Bit 1 : when 0 => normal ADC data else testpattern data Bit 0 : when 0 => 0x3FFF -> 0x0000 else 0x2AAA -> 0x1555
