SU750

SU750 pin table (direction shown for the SU board!)

 power    in            +5V  2    1 +5V             in     power
 LVTTL bidir            SDA  4    3 SCL             in     LVTTL
 LVTTL   out        DATA<1>  6    5 DATA<0>         out    LVTTL
 LVTTL   out        DATA<3>  8    7 DATA<2>         out    LVTTL
 LVTTL   out        DATA<5> 10    9 DATA<4>         out    LVTTL
 LVTTL   out        DATA<7> 12   11 DATA<6>         out    LVTTL
 LVTTL   out        DATA<9> 14   13 DATA<8>         out    LVTTL
 LVTTL   out       DATA<11> 16   15 DATA<10>        out    LVTTL
 LVTTL   out       DATA<13> 18   17 DATA<12>        out    LVTTL
 LVTTL    in          TRIGG 20   19 VALID           out    LVTTL
 LVTTL    in        FREQ<2> 22   21 SPI_CONF        in     LVTTL
 LVTTL    in        FREQ<1> 24   23 FREQ<0>         in     LVTTL
 LVTTL    in          RESET 26   25 CLK_READ        in     LVTTL
 LVTTL   out           SDRD 28   27 SEn             in     LVTTL
 LVTTL    in          SCLKn 30   29 SDATA           in     LVTTL
 LVTTL   out        PGND<1> 32   31 PGND<0>         out    LVTTL
 LVTTL    in           CLKp 34   33 CLKn            in     LVTTL
 power    in            GND 36   35 GND             in     power

Differences to SU735:

• ADC

SU735         SU750
LTC2261       ADS4149

• Pinout

SU735              SU750            PIN
GI_GATE (in)       VALID (out)      19
SPARE<1>           TRIGG (in)       20
SPARE<2>           SPI_CONF (in)    21
SPARE<3>           FREQ<2> (in)     22 (still not used in design)
CLK_CPU            CLK_READ         25 (was not used in the latest firmware of SU735)
-                  GND              31, 32

• SU750 should get ALWAYS 100 MHz at CLKp and CLKn!

• CLK_READ can be 100 MHz or below, it is used to clock out the data from the internal memory

• VALID = 1 means valid output data (SU750), SU735 forwards directly the ADC data.

• TRIGG = 1 starts the data storing, shortly after triggering the readout is started as a complete block, with VALID=1 indicatiing valid data.

• SPI_CONF = 1 selects the internal configuration registers instead of the ADC (and disconnects the ADC SPI).

The SPI Word has 16 bits (like of the ADC), the upper 3 (MSB) bits are address, the next bit is read(0) or write(1), the other 12 (LSB) bits are data.

SPI configuration registers:

• PRESAMPLE (10 bits) at 0

• EVNT_SIZE (3 bits) at 1

evnt_size    Event Size[samples]
  000                16
  001                32
  010                64
  011               128
  100               256
  101               512
  110              1024
  111              1024 (later 2048)

• LED (7 bits) at 2

Bits 0..4 are for LEDs from top to bottom.
Bit 5: when 0, display the "ok" of test pattern check for 0x2AAA -> 0x1555, else LED=Bit 3
Bit 6: when 0, display the "ok" of test pattern check for ramp, else LED=Bit 4

• SEND_TP (2 bits) at 3

Bit 1 : when 0 => normal ADC data else testpattern data
Bit 0 : when 0 => 0x3FFF -> 0x0000 else 0x2AAA -> 0x1555

This test pattern is send at 100 MHz (CLK_READ) continuously by the FPGA and can be checked in the LogicBox.

• FREQ_CNT at 4

Read the ADC clocks for 1000 logic box (CLK_READ) clocks => divide by 10 to get the freq in MHz (provided CLK_READ is 100 MHz).

• TP_CHECK at 5

Bit 1 : ok for ramp pattern from ADC
Bit 0 : ok for 0x2AAA -> 0x1555 pattern from ADC

This test pattern is send by the ADC and checked continuously in the FPGA for errors. The flags are cleared by any error and can be set by writing anything to this address. So the typical test procedure is 1) set the frequency and test pattern in ADC; 2) wait a bit and clear the errors by writing to TP_CHECK; 3) wait some seconds (or more) and read the two flags.