SU700

This module has 5 independent 3.3V TTL input/output, each of this IOs is provided with a LEMO connector. The signals can be configured as input or output through a FPGA register. Each channel can drive current up to 60 mA, in this way a 50 Ohm terminated cable can be use to avoid reflections. Meter la frecuencia máxima de conmutación. If the IO was configured as input a 50 Ohm resistor can be parallel connected to the input to avoid reflections, this can be done through a FPGA register.

A pull up resistor can be populated in each channel if needed. In this function mode the 50 Ohm resistor must be not connected.

The submodule contains 5 LEDs, witch are direct connected to FPGA outputs, the LEDs can be configured through internal registers.

Pinout

SU700 pin table (direction shown for the SU board)

 power    in            +5V  2    1 +5V             in     power
 LVTTL    in        DOUT<4>  4    3 DIN<5>          out    LVTTL
 LVTTL    in        DOUT<5>  6    5 DOEn<5>         in     LVTTL
 LVTTL    in        DOEn<4>  8    7 -               -      NC
 LVTTL    in        DOUT<3> 10    9 DIN<4>          out    LVTTL
 LVTTL    in        DOEn<3> 12   11 DIN<3>          out    LVTTL
 LVTTL    in        DOUT<2> 14   13 DIN<2>          out    LVTTL
 LVTTL    in        DOEn<2> 16   15 DIN<1>          out    LVTTL
 LVTTL    in        DOUT<1> 18   17 DOEn<1>         in     LVTTL
 LVTTL    in        LEDn<5> 20   19 LEDn<4>         in     LVTTL
 LVTTL    in        LEDn<3> 22   21 LEDn<2>         in     LVTTL
    NC     -              - 24   23 LEDn<1>         in     LVTTL
    NC     -              - 26   25 -               -      NC
    NC     -              - 28   27 -               -      NC
    NC     -              - 30   29 -               -      NC
    NC     -              - 32   31 -               -      NC
    NC     -              - 34   33 -               -      NC
 power    in            GND 36   35 GND             in     power

DIN<n> - Input channel n

DOUT<n> - Output channel n

DOEn<n> - Output enable (active low) channel n

LEDn<n> - LED n (active low)

LogicPool

 IO

 read
 
   when 0	=> DOut <= ModuleID(Version,Model,NBase,Outp_TIG);
 
 write
 
   when 0 	=> AMux_TIG         <= Conv_Integer(DIn(7 downto 0));
   when 1 	=> Termination_TIG  <= DIn(0);  -- when 2 for compatibility
                  NIM_TIG          <= DIn(1);
 
 if Reset='1' then
   AMux_TIG <= 0;
   Termination_TIG <= '0';
   NIM_TIG <= '0';
 end if;

 LED

 read
   when 0	=> DOut <= ModuleID(Version,Model,0,'0');
 
 write
   model 0
     when 0 		=> AMux_TIG <= Conv_Integer(DIn(7 downto 0));
   model 1
     when 0 		=> AMux_TIG <= Conv_Integer(DIn(7 downto 0));
     when 1		=> Divider_TIG <= Conv_Integer(DIn(23 downto 0));
                          Clear <= true;