Difference between revisions of "SU707"
(→Description) |
|||
| Line 1: | Line 1: | ||
= Description = | = Description = | ||
| + | |||
| + | |||
| + | This module family consists of 8 LVDS digital input output (DIO). As connectors is used two RJ45, so the user can use a standard patch cable to send/receive information. | ||
| + | |||
| + | == Version 0 == | ||
| + | |||
| + | has to group of 4 channels, you can populated each group as input or output. If the transceiver and receiver for one group are populated, you can dynamically set the group as input or output, but the driver will create only the half voltage. | ||
| + | |||
| + | sender ic : SN75LVDS391PW, speed up to 200 Mbps, typical output voltage 350 mV @ 100 Ohm load (for more details see datasheet) | ||
| + | receiver ic: SN75LVDS390PW, speed up to 200 Mbps, detects 100mV (for more details see datasheet) | ||
= Block Diagram = | = Block Diagram = | ||
Revision as of 15:42, 5 September 2014
Contents
Description
This module family consists of 8 LVDS digital input output (DIO). As connectors is used two RJ45, so the user can use a standard patch cable to send/receive information.
Version 0
has to group of 4 channels, you can populated each group as input or output. If the transceiver and receiver for one group are populated, you can dynamically set the group as input or output, but the driver will create only the half voltage.
sender ic : SN75LVDS391PW, speed up to 200 Mbps, typical output voltage 350 mV @ 100 Ohm load (for more details see datasheet) receiver ic: SN75LVDS390PW, speed up to 200 Mbps, detects 100mV (for more details see datasheet)
Block Diagram
Version 0
Front panel
Version 0
| Pos (top view) | Name | Type | Qty. | Dir. | Function |
|---|---|---|---|---|---|
| 1 LEFT/RIGHT/MIDDLE | Analog input | LEMO connector | 1x | input | Detector input |
| 2 LEFT/RIGHT/MIDDLE | DIO | LEMO connector | 1x | input/output | Digital input/output (LVTTL) |
Back Connector
Version 0
SU707 pin table (direction shown for the SU board!)
power in +5V 2 1 +5V in power
LVTTL out LVDS_I<1> 4 3 LVDS_I<2> out LVTTL
LVTTL in LVDS_O<1> 6 5 LVDS_O<2> in LVTTL
LVTTL in LVDS_O<3> 8 7 LVDS_O<4> in LVTTL
LVTTL out LVDS_I<3> 10 9 LVDS_I<4> out LVTTL
LVTTL out LVDS_I<5> 12 11 LVDS_I<6> out LVTTL
LVTTL in LVDS_O<5> 14 13 LVDS_O<6> in LVTTL
LVTTL in LVDS_O<7> 16 15 LVDS_O<8> in LVTTL
LVTTL out LVDS_I<7> 18 17 LVDS_I<8> out LVTTL
LVTTL in EN_O<2> 20 19 EN_I<2> in LVTTL
LVTTL in EN_O<1> 22 21 EN_I<1> in LVTTL
NC - - 24 23 - - NC
NC - - 26 25 - - NC
NC - - 28 27 - - NC
NC - - 30 29 - - NC
NC - - 32 31 - - NC
NC - - 34 33 - - NC
power in GND 36 35 GND in power
Version 1
power in +5V 2 1 +5V in power LVTTL in LVDS_O<1> 4 3 EN_O<1> in LVTTL LVTTL in LVDS_O<2> 6 5 EN_O<2> in LVTTL LVTTL in LVDS_O<3> 8 7 - - NC LVTTL in LVDS_O<4> 10 9 - - NC LVTTL out LVDS_I<1> 12 11 EN_I<1> in LVTTL LVTTL out LVDS_I<2> 14 13 EN_I<2> in LVTTL LVTTL out LVDS_I<3> 16 15 LED<1> in LVTTL LVTTL out LVDS_I<4> 18 17 LED<2> in LVTTL LVTTL in LVDS_O<5> 20 19 EN_O<3> in LVTTL LVTTL in LVDS_O<6> 22 21 EN_O<4> in LVTTL LVTTL in LVDS_O<7> 24 23 - - NC LVTTL in LVDS_O<8> 26 25 - - NC LVTTL out LVDS_I<5> 28 27 EN_I<3> in LVTTL LVTTL out LVDS_I<6> 30 29 EN_I<4> in LVTTL LVTTL out LVDS_I<7> 32 31 - - NC LVTTL out LVDS_I<8> 34 33 - - NC power in GND 36 35 GND in power
Version 2
power in +5V 2 1 +5V in power
LVTTL in LVDS_O<1> 4 3 EN_O<1> in LVTTL
LVTTL in LVDS_O<2> 6 5 EN_O<2> in LVTTL
LVTTL in LVDS_O<3> 8 7 - - NC
LVTTL in LVDS_O<4> 10 9 - - NC
LVTTL out LVDS_I<1> 12 11 EN_I<1> in LVTTL
LVTTL out LVDS_I<2> 14 13 EN_I<2> in LVTTL
LVTTL out LVDS_I<3> 16 15 LED<1> in LVTTL
LVTTL out LVDS_I<4> 18 17 LED<2> in LVTTL
LVTTL in LVDS_O<5> 20 19 EN_O<3> in LVTTL
LVTTL in LVDS_O<6> 22 21 EN_O<4> in LVTTL
LVTTL in LVDS_O<7> 24 23 - - NC
LVTTL in LVDS_O<8> 26 25 - - NC
LVTTL out LVDS_I<5> 28 27 EN_I<3> in LVTTL
LVTTL out LVDS_I<6> 30 29 EN_I<4> in LVTTL
LVTTL out LVDS_I<7> 32 31 LVDS_I<8> out LVDS
NC - - 34 33 - - NC
power in GND 36 35 GND in power
Power consumption
Version 0
+5V -> XX mA -5V -> XX mA
