Time to digital converter (TDC)

LogicPool (TDC)

This module is a software implementation, no need of hardware to work. The TDC will capture the time stamp of the input channels by rising edge so long the gate is activated. The maximal time resolution is 10 ns and can be changed through a programmable divider, an external signal can be used as TDC clock too.

This module has a bus interface to connect with a FIFO, in this FIFO will be written the channel and time information of each rising edge, so long the gate is active. The number of channels and length of the time stamp counters depends on the selected model.

During the gate a package will be written in the FIFO. This package can consists of a Start of gate marker, 0 to N events marker and a stop of gate marker.

Versions

05.04.11 V1.0
07.04.11 Extended with Timebase and 8 Channels
29.04.11 EOG recording added
01.07.11 V1.1: 1 Channel Version with 32b Time added
18.08.11 V1.2: TimeReg cleared on read
21.02.12 V1.3: DisableEOG implemented
22.02.12 V1.4: TriggerMode with Retrigger implemented
24.02.12 V1.5: SOG & EOG control independent of Mode
28.01.15 V1.6: SOG & EOG bug fixed, now is really working
               Programmable delay between channel input and gate signal implemented

Models

At this time there are two models. The model 0 has only one event channel and the model 1 8 event channels. The event marker are different for each model. The model 0 event marker is a 32-bits time information and the model 1 event marker consist of 8-Bit channel mask to indicate which channels has been toggle and 24-bit with the time stamp

TDC model 1 Package overview

Event	Channel info (bits 31..24)	Time stamp (bits 23..0)	Explanation
SOG	0x00	0x000000	SOG = start of gate, time stamp will be always 0 and no active channels
E1	0x01	0x000064	detected a rising edge on channel 0 100 CLKs after the SOG
E2	0x03	0x000080	detected a rising edge on channel 0 and 1 128 CLKs after the SOG
E3	0x00	0xFFFFFF	time stamp counter overflow
E4	0x80	0x0001FF	detected a rising edge on channel 7 16777215+511 CLKs after the SOG
EOG	0x00	0x0003FF	EOG = end of gate, no active channels and time stamp must be non zero

CBUS Address

Register Map Model 0

Module Address: 'B' or Ox42

Read register

Read registers

Register Address	Name	Data
0	MUX_IN	Bit 7..0: multiplexer address
1	EVENT MARKER	Bit 31..0: current event information

Write register

Write registers

Register Address	Name	Data
0	MUX_GATE	Bit 7..0: gate multiplexer address
1	MUX_CLOCK	Bit 7..0: clock multiplexer address
2	CLOCK_DIVIDER	Bit 31..0:
3	MUX_EVENT_CHANNEL	Bit 7..0: event channel multiplexer address
11	CONF_REG	Bit 0: disable end of gate (EOG) Bit 1: disable start of gate (SOG) Bit 2: retrigger
12	GATE_TIME	Bit 31..0: if this value is set to 0 the end of gate will be controlled through the gate input, otherwise the gate will be a duration of this value x clock period
13	DATA_DELAY	Bit 2..0: create a delay between the gate and the input event channels.

Register Map Model 1

Module Address: 'B' or Ox42

Read register

Read registers

Register Address	Name	Data
0	MUX_IN	Bit 7..0: multiplexer address
1	EVENT MARKER	Bit 31..0: current event information

Write register

Write registers

Register Address	Name	Data
0	MUX_GATE	Bit 7..0: gate multiplexer address
1	MUX_CLOCK	Bit 7..0: clock multiplexer address
2	CLOCK_DIVIDER	Bit 31..0:
3	MUX_EVENT_CHANNEL_0	Bit 7..0: event channel 0 multiplexer address
4	MUX_EVENT_CHANNEL_1	Bit 7..0: event channel 1 multiplexer address
5	MUX_EVENT_CHANNEL_2	Bit 7..0: event channel 2 multiplexer address
6	MUX_EVENT_CHANNEL_3	Bit 7..0: event channel 3 multiplexer address
7	MUX_EVENT_CHANNEL_4	Bit 7..0: event channel 4 multiplexer address
8	MUX_EVENT_CHANNEL_5	Bit 7..0: event channel 5 multiplexer address
9	MUX_EVENT_CHANNEL_6	Bit 7..0: event channel 6 multiplexer address
10	MUX_EVENT_CHANNEL_7	Bit 7..0: event channel 7 multiplexer address
11	CONF_REG	Bit 0: disable end of gate (EOG) Bit 1: disable start of gate (SOG) Bit 2: retrigger
12	GATE_TIME	Bit 31..0: if this value is set to 0 the end of gate will be controlled through the gate input, otherwise the gate will be a duration of this value x clock period
13	DATA_DELAY	Bit 2..0: create a delay between the gate and the input event channels.

LabVIEW Vi

Global parameters

This parameters must always be connected

TDC#: number of module (must be unique)
USB In and USB Out are related to the selected USB interface, No connection uses a global parameter, set by OPEN.vi!

Signal inputs

A signal input, is a hardware input which control some functionality of the module.

 GATE: gate drive signal (address of the signal which will drive this input)  
 CLOCK: clock drive signal (address of the signal which will drive this input). If 0 the 100 MHz internal clock will be used.
 CHANNEL: array of channel drive signals (addresses of the signals which will drive this inputs)

Signal outputs

A signal output, is a hardware output which can drive one or more signal inputs. For example a clock generator can drive 2 DIOs

 no signals outputs in this module

Functions and parameters

In the LogicPool Vis there is always a input terminal with a parameter called function. This parameter select the function that the user want to call and for this propose need sometimes parameters (input terminals). Here will be listed the function and the parameters that the user should use with each function. If the parameters are not set the last saved parameters will be used and not desired behaviour can happen.

 "Write PARAMS"
 Set the acquisition parameters of the TDC. 
   Parameters:
     Params: cluster compose of:
        SOG: type boolean, if active a Start of gate marker will be written into the FIFO by rising edge of the Gate input signal
        EOG:  type boolean, if active a End of gate marker will be written into the FIFO by falling edge of the Gate input signal or when the gate time is over if GATE TIME is non zero. 
        GATE TIME: type 32-Bit unsigned integer. If non zero the falling edge of the Gate input signal will be ignored, and this value will be used to generate the end of gate.
        DIVIDER: type 32-Bit unsigned integer. divider of the input clock.

 "Set GATE"
 Connect the gate input signal with a driver module or set it to a constant value.
   Parameters:
     GATE: type 8-bit unsigned. At this input should be connected the output of the driver module. 
           You can set this input to a constant value through LabVIEW with the help of the B_S subvi.

 "Set CLOCK"
 Connect the clock input signal with a driver module or set it to a constant value.
   Parameters:
     CLOCK: type 8-bit unsigned. At this input should be connected the output of the driver module. 
            You can set this input to a constant value through LabVIEW with the help of the B_S subvi.

 "Set CHANNEL"
 Connect the clock input signal with a driver module or set it to a constant value.
   Parameters:
     CHANNEL: type array of 8-bit unsigned. At this input should be connected and array with the output of the 
              driver modules. You can set this input to a constant value through LabVIEW with the help of the B_S subvi.

 "Get BUS"
 Get the state of the write signal of the bus, this BUS consist of write signal + 32-Bit data

 "Read Event"
 Read the last marker.

 "Set data delay"
 Create a delay between the gate input signals and the input channels signals. This functionality is implemented in version 1.6 and higher.
   Parameters:
      DataDelay: type 8-Bit unsigned. The delay can be set between 0 and 7.  

 "Connect" connects all signal inputs if any, and initialize the module 
   Parameters:
     CHANNEL
     GATE
     CLOCK
     Params

Demo software

At this moment only the LP_TDC_1_Test.vi is working with the last LabVIEW version. Following modules are needed to test the TDC:

1 x TDC 1 x FIFO 3 x Gate generators 4 x LEDs 3 x DIOs