SU717

Description

This module is a charge to digital converter. It consists of 3 blocks:

 1) Front end (Signal conditioning)
 2) FPGA controlled integrator
 3) Analog to digital converter

The front end consist of a LEMO connector and after that can be found a RF transformer or a capacitor, or can be connected direct to the integrator input. The detector signal should be ac coupled to avoid dc errors.

The integrator is based on an operation amplifier and a TTL controlled switch to reset the capacitor charge. In this way the integration time can be set through an external control signal.

The last stage is a 14-Bit analog to digital converter and it can be run up to 100MHz from Texas instruments ADS5500. All ADC control and data signals are routed to the sub-module back connector.

Back Connector

Version 0

SU717 pin table (direction shown for the SU board!)

 power    in            +5V  2    1 +5V             in     power
 LVTTL    in          RESET  4    3 CLKout          out    LVTTL
 LVTTL   out        DATA<0>  6    5 DATA<1>         out    LVTTL
 LVTTL   out        DATA<2>  8    7 DATA<3>         out    LVTTL
 LVTTL   out        DATA<4> 10    9 DATA<5>         out    LVTTL
 LVTTL   out        DATA<6> 12   11 DATA<7>         out    LVTTL
 LVTTL   out        DATA<8> 14   13 DATA<9>         out    LVTTL
 LVTTL   out       DATA<10> 16   15 DATA<11>        out    LVTTL
 LVTTL   out       DATA<12> 18   17 DATA<13>        out    LVTTL
    NC     -              - 20   19 SCLKn           in     LVTTL
 LVTTL    in          SDATA 22   21 SEn             in     LVTTL
 LVTTL    in           CLKp 24   23 CLKn            in     LVTTL
 LVTTL    in        DIO_OUT 26   25 DIO_OEn         in     LVTTL
 LVTTL    in        QRESETn 28   27 DIO_IN          out    LVTTL
 LVTTL    in        QSHORTn 30   29 -               -      NC
    NC     -              - 32   31 LEDn            in     LVTTL
    NC     -              - 34   33 -               -      NC
 power    in            GND 36   35 GND             in     power