LP module

LogicPool (QDC)

A brief introduction: This VHDL module needs a SU7XX hardware sub-module to work.... This module is software implementation, no need of hardware to work.....

Models

There is only one model for this module.

CBUS Address

Supported Hardware

SU7XX Just a link to the hardware module if any

Register Map

Module Address: 'T' or Ox??

Read register

Read registers

Register Address	Name	Data
0	MUX_IN	Bit 7..0: multiplexer address
1	STATE_IN	Bit 7..0: input value

Write register

Write registers

Register Address	Name	Data
0	MUX_OUT	Bit 7..0: multiplexer address
1	Debounce	Bit 7..0: input value
2	Mode	Bit 0: '1' 50 Ohm termination '0' Open Bit 1: NIM/TTL '1' NIM '0' TTL

Read/Write register

Read/Write registers

Register Address	Name	Data
0	MUX_IN	Bit 7..0: multiplexer address
1	STATE_IN	Bit 7..0: input value

LabVIEW Vi

Inputs

 Input 1: 
 Input 2:

Outputs

 Output 1: 
 Output 2:

Parameters

 Param 1: 
 Param 2:

Functions

 Function 1: 
 Function 2: