SU741
SU741 pin table (direction shown for the SU board!)
power in +5V 2 1 +5V in power
LVTTL bidir D<1> 4 3 D<0> bidir LVTTL
LVTTL bidir D<3> 6 5 D<2> bidir LVTTL
LVTTL bidir D<5> 8 7 D<4> bidir LVTTL
LVTTL bidir D<7> 10 9 D<6> bidir LVTTL
LVTTL bidir D<9> 12 11 D<8> bidir LVTTL
LVTTL bidir D<11> 14 13 D<10> bidir LVTTL
LVTTL bidir D<13> 16 15 D<12> bidir LVTTL
LVTTL bidir D<15> 18 17 D<14> bidir LVTTL
LVTTL in REQ 20 19 READ_n in LVTTL
LVTTL in Addr<1> 22 21 Addr<0> in LVTTL
LVTTL in CMD_n 24 23 Sync in LVTTL
LVTTL out READY 26 25 CLK in LVTTL
LVTTL in DAC 28 27 FCLR in LVTTL
* in LDACn 30 29 SPI_SDO_CLR out *
* in SPI_CLK 32 31 SPI_DIN2 in *
* in SPI_DIN1 34 33 SPI_Sync_n in *
power in GND 36 35 GND in power
- Note: when FCLR is 1, the DAC and SPI signals (pin29..pin34) can be driven from the LogicBox.
Otherwise the LogicBox should NOT drive these 6 signals! They are driven by the FPGA on SU741!
Differences to SU730 as till Feb 2014:
- the memory is 4M x 16 instead of 8M x 16
- there is a direct connection to the SPI and DAC interface
- no HISTO and CRE signals on the SU-connector (CRE was anyway not used)
- Addr2 is now Sync (10 MHz for time measurement), therefore 2 instead of 4 address pointers
- DAC signal has another meaning (was anyway not used before)
- control/command/status registers - still not fully defined and implemented, used for start/pause/stop and more.
Interface:
req cmd_n iaddr1 iaddr0 read_n dac fclr Bits Name Comment x x x x x x 1 x - clear address counters and state machines, tri-state the SPI signals 1 0 N=0..1 0 1 0 0 16 AC0..1 write bits 15.. 0 of address counter N, AC[N][15..0]=DI 1 0 N=0..1 1 1 0 0 6 AC0..1 write bits 21..16 of address counter N, AC[N][21..16]=DI[5..0] 1 0 N=0..1 0 0 0 0 16 AC0..1 read lower part of address counter: DO=AC[N][15..0] 1 0 N=0..1 1 0 0 0 6 AC0..1 read upper part of address counter: DO[5..0]=AC[N][21..16] ---------------------------------------------------------- 1 0 N=0..3 1 1 0 16 CR0..3 write control/command register CR[N] 1 0 N=0..3 0 1 0 16 CR0..3 read control/command/status register CR[N] ---------------------------------------------------------- 1 1 N=0..1 0 1 0 0 16 memory write: mem[AC[N]]=DI 1 1 N=0..1 1 1 0 0 16 memory write with address increment: mem[AC[N]]=DI, AC[N]++ ---------------------------------------------------------- 1 1 N=0..1 0 0 0 0 16 memory read: DO=mem[AC[N]] 1 1 N=0..1 1 0 0 0 16 memory read with address increment: DO=mem[AC[N]], AC[N]++ ---------------------------------------------------------- ---------------------------------------------------------------------
DI are the data coming from the Logic Box DO are the data to the Logic Box
sync is a slow clock (10 MHz) for the time measurement
Bit positions writing to CR[0] : 0 : start from the beginning, 1 : pause, 2 : stop ... DI/DO 0..15 read_n 16 req 17 iaddr 18..19 sync 20 cmd_n 21 clk 22 ready 23 fclr 24 dac 25
How to operate:
1) init both address pointers with the same (either with fclr or by writing to AC[0] and AC[1])
2) write the memory content with address autoincrement using e.g. AC[1]
3) start the sequency by writing to the CR[0] (to be defined in details)
4) later reading status from CR is allowed, but memory read/write is blocked while running the sequence
Most used DAC values (the default values are all 0)
R/nW Z REG A DATA
23 22 21..19 18..16 15..0
0 0 0 0 0 dac# value : set dac# value, for 14 bit DAC the two LSBs are don't care, for 12 bit DAC the 4 LSBs are don't care.
0 0 0 0 1 dac# range : set output range of dac#, 0 1 2 3 4 5
: 5V 10V 10.8V +/-5V +/-10V +/-10.8
0 0 0 1 0 0 0 0 power : set bits 0..3 to power up DAC 0..3 (default is off and this reg must be set)
0 0 0 1 1 0 0 0 - : NOP (= 0x18XXXX)
0 0 0 1 1 0 0 1 control : Bit 3 is TSD (thermal shutdown enable), Bit 2 is current-limit clamp enable
: Bit 1 is Clear select 0: clear to 0V, 1: clear to midscale (unipolar) or negative full scale (bipolar)
: Bit 0 is SDO disable
0 0 0 1 1 1 0 0 - : clear, update the DAC register with the clear code and set the outputs
0 0 0 1 1 1 0 1 - : load, update the DAC register and set the outputs
when control reg!
DACC[15..13] -> SPI_DATA[21..19] DACC[12..10] -> SPI_DATA[18..16] DACC[ 3.. 0] -> SPI_DATA[ 3.. 0]
001XXXXXXXXXX000 -> 5V 001XXXXXXXXXX001 -> 10V 001XXXXXXXXXX010 -> 10.8V 001XXXXXXXXXX011 -> +/-5V 001XXXXXXXXXX100 -> +/-10V 001XXXXXXXXXX101 -> +/-10.8
010XXXXXXXXX0000 -> DAC 3..0 off 010XXXXXXXXX1111 -> DAC 3..0 on 010XXXXXXXXX0101 -> DAC 0 and DAC 2 on
RAM information
Bits
15 14 0 Comment
1 < time_step[30..16] > 31-bit time step to the next DAC update
< time_step[15.. 0] > Special words:
0xFFFF FFFF - pause,
0x8000 0000 - stop
0xFFFF FFFE - send immediately
0 0 < divider[29..16] > Program divider for the time_step
< divider[15.. 0] >
0 1 < command[5..0]> < ADCmask[7..0] > command = 0 : DAC config register
command = 1 : DAC output register
< DAC output MSB non-zero bit in mask >
...
< DAC output LSB non-zero bit in mask >
Example:
Addr Data Comment
0 0x0000 Set time step divider
1 0x0064 to 100 (1 us step in internal clock mode)
2 0x40FF Set DAC control registers in all DACs
3 DACC[0]
.. ..
10 DACC[7]
11 0x41FF Set the initial DAC values in all DACs
12 DACI[0]
.. ..
19 DACI[7]
20 0xFFFF pause, wait for the trigger to continue
21 0xFFFF
22 0x8000
23 0x000A time step 10 us
24 0x4131 DAC output value will follow, for DACs 0, 4, 5.
25 DAC[0]
26 DAC[4]
27 DAC[5]
28 0x000A time step 10 us
.. ...
0x8000 stop
0x0000
There are two SPI interfaces, running in parallel: Group 0: DAC channels 0..3 Group 1: DAC channels 4..7
For highest update speed distribute the used channels equally in the two groups.
E.g. when using channels 1,2,4,7 the update speed will be higher than when using 0,1,2,3.
