Time to digital converter (TDC)
Contents
LogicPool (TDC)
This module is a software implementation, no need of hardware to work. The TDC will capture the time stamp of the input channels by rising edge so long the gate is activated. The maximal time resolution is 10 ns and can be changed through a programmable divider, an external signal can be used as TDC clock too.
This module has a bus interface to connect with a FIFO, in this FIFO will be written the channel and time information of each rising edge, so long the gate is active. The number of channels and length of the time stamp counters depends on the selected model.
During the gate a package will be written in the FIFO. This package can consists of a Start of gate marker, 0 to N events marker and a stop of gate marker.
Models
At this time there are two models. The model 0 has only one event channel and the model 1 8 event channels. The event marker are different for each model. The model 0 event marker is a 32-bits time information and the model 1 event marker consist of 8-Bit channel mask to indicate which channels has been toggle and 24-bit with the time stamp
Supported Hardware
SU7XX Just a link to the hardware module if any
Register Map
Module Address: 'T' or Ox??
Read register
| Register Address | Name | Data |
|---|---|---|
| 0 | MUX_IN | Bit 7..0: multiplexer address |
| 1 | STATE_IN | Bit 7..0: input value |
Write register
| Register Address | Name | Data |
|---|---|---|
| 0 | MUX_OUT | Bit 7..0: multiplexer address |
| 1 | Debounce | Bit 7..0: input value |
| 2 | Mode | Bit 0:
'1' 50 Ohm termination '0' Open Bit 1: NIM/TTL '1' NIM '0' TTL |
Read/Write register
| Register Address | Name | Data |
|---|---|---|
| 0 | MUX_IN | Bit 7..0: multiplexer address |
| 1 | STATE_IN | Bit 7..0: input value |
LabVIEW Vi
Inputs
Input 1: Input 2:
Outputs
Output 1: Output 2:
Parameters
Param 1: Param 2:
Functions
Function 1: Function 2:
