SU751

SU751 can accomodate 5 small sub-modules (here numbered from 1 to 5), each connected thorugh 3 I/Os to the SU751 connector and so to the FPGA.

Pin table (direction shown for the SU board!)

power    in            +5V  2    1 +5V             in     power
LVTTL    in        OUTP<5>  4    3 INP<5>          out    LVTTL
LVTTL    in        OE_n<5>  6    5 INJ<5>
  GND    in            GND  8    7 LED_n<5>        in     LVTTL
LVTTL    in        OUTP<4> 10    9 INTTL<4>        out    LVTTL
LVTTL    in        OE_n<4> 12   11 INJ<4>
  GND    in            GND 14   13 LED_n<4>        in     LVTTL
LVTTL    in        OUTP<3> 16   15 INTTL<3>        out    LVTTL
LVTTL    in        OE_n<3> 18   17 INJ<3>
  GND    in            GND 20   19 LED_n<3>        in     LVTTL
LVTTL    in        OUTP<2> 22   21 INTTL<2>        out    LVTTL
LVTTL    in        OE_n<2> 24   23 INJ<2>
  GND    in            GND 26   25 LED_n<2>        in     LVTTL
LVTTL    in        OUTP<1> 28   27 INTTL<1>        out    LVTTL
LVTTL    in        OE_n<1> 30   29 INJ<1>
  GND    in            GND 32   31 LED_n<1>        in     LVTTL
   NC     -              - 34   33 GND             -      GND
power    in            GND 36   35 GND             in     power

Note: 1) INJ<1..5> can be jumpered on SU751 to INP<1..5> in order to be fullly compatible to SU704. Normally not necessary. 2)The additional GND pins can be connector in the FPGA as outputs driving 0. Be carefull not to drive 1! 3) The LEDs are active low, like in SU704.

List of the sub-modules for SU751.

A-0: Comparator with LT1719, the threshold can be bipolar and set by resistors. The output of the comparator is high when the input is higher than the threshold and is mapped to the INP<n> port. OE_n<n> and OUTP<n> are not connced.

A-1: